1. Field of the Invention
The present invention relates to a structure of a semiconductor device having a bonding pad, particularly to a structure of a semiconductor device for increasing strength against a stress applied to the bonding pad in probing and wire bonding.
2. Description of the Background Art
A mechanical stress is applied to a bonding pad formed on a top surface of a semiconductor chip during probing in an electric test of a semiconductor chip or during wire bonding in assembling a semiconductor device. The stress applied to the bonding pad possibly causes generation of a crack in an interlayer insulator below the bonding pad or generation of peel-off of the bonding pad during wire bonding.
A crack is generated in the interlayer insulator below the bonding pad by the stress applied from outside to the bonding pad. In a case where the crack reaches a lower-layer interconnection, deterioration occurs to a metal migration-resistant property of the interconnection. In a structure in which the interconnection is provided so as to pass below the bonding pad, strength thereof is relatively weak and a crack is easily generated. Therefore, disposition of an active element tends to be avoided. Accordingly, in order to prevent generation of a crack, desirably the interconnection and the active element do not carelessly pass below the bonding pad.
However, in order to achieve high integration of the semiconductor device, it is necessary that a semiconductor substrate be effectively utilized by using a region below the bonding pad. Therefore, it is inevitable that the interconnection and the active element are provided below the bonding pad. For example, WO2005/083767 discloses a structure of a semiconductor device in which strength against a stress applied from outside to a bonding pad is enhanced while achieving high integration of the semiconductor device.
The structure of the semiconductor device disclosed in WO2005/083767 adopts a configuration in which at least five interconnection layers are provided below the bonding pad in a case where an interconnection and an active element are provided below the bonding pad (see FIGS. 44 and 45 of WO2005/083767). The stress applied from outside to the bonding pad is dispersed by adopting the structure, and stress concentration on a particular point is relieved to restrain deterioration in semiconductor device strength to a minimum, thereby allowing the high integration of the semiconductor device.
However, because the deterioration in semiconductor device strength is restrained to a minimum, a production cost of the semiconductor device is increased in a case where at least five interconnection layers are provided. On the other hand, there is another method in which the stress applied to the bonding pad is strictly managed on a production apparatus side to decrease the number of interconnection layers during the probing in the electric test of the semiconductor chip or during the wire bonding in assembling the semiconductor device. However, in a case of adopting the method, productivity of the semiconductor device is largely sacrificed. Therefore, even in a case where this method is adopted, the production cost of the semiconductor device is increased.
Accordingly, the problem to be solved by the invention is that the production cost of the semiconductor device is increased when the stress concentration applied from outside on the particular point of the bonding pad of the semiconductor device is relieved to restrain the deterioration in semiconductor device strength to a minimum.